The present invention relates to a microprocessor and, more particularly, to a pipelined microprocessor having a branch prediction function.
An instruction prefetch function and a pipelined processing function are widely used to enhance the program execution efficiency of a microprocessor. However, when the microprocessor encounters a unconditional or conditional branch instruction, the execution efficiency thereof are often lowered remarkably. This is because the branch instruction changes the instruction stream to be executed, so that the address to be accessed by the instruction prefetch function is changed with suspending the pipelined processing operation.
In order to solve this drawback, therefore, a branch prediction function is provided to the microprocessor. In this function, a branch prediction table is provided to store in pairs an address of a branch instruction and a branch address designated by the branch instruction. When the branch instruction is prefetched, therefore, a branch prediction hit signal is derived from the table. In response to the hit signal, an instruction stored in the branch address, i.e. branch target instruction, is prefetched in place of prefetching instructions succeeding to the branch instruction. The disturbance in the pipelined processing operation is thus prevented or suppressed.
However, the following problem rises in turn in a recent high performance microprocessor. Specifically, a microprocessor performs in general a data processing operation in word units, so that the instruction prefetch operation is also performed in word units. In a recent high performance microprocessor, the bit length of one word is expanded. Assuming that one word is constructed of 32 bits, instruction data is fetched in 4-byte units per one prefetch operation. The fact that the instruction prefetch operation is performed in 4-byte units means that the memory access for prefetching respective instructions is performed with disregarding the less significant two bits (including the least significant bit) of the address. On the other hand, the byte length of respective instructions including the branch target instruction is not constant, but changes depending on the required data processing operation and/or the addressing mode for operand data. For this reason, the leading byte of each instruction is not always coincident with the word boundary. That is, the leading byte of the branch target instruction is often different from the first byte of four bytes fetched in fact by the prefetch operation for the branch target instruction. Accordingly, such information is required that represents which byte of four bytes fetched in fact corresponds to the leading byte of the branch target instruction. Without this information, the decoding operation on the branch target instruction is delayed and disturbs the pipelined processing operation.
Moreover, a recent program has been complicated to comply with a higher level processing operation, and in such a program a branch instruction is often written in the branch address. That is, the branch target instruction may be also a branch instruction for requiring a further branch target instruction. In this case, unless there is information for representing which byte of four bytes fetched in fact by the prefetch operation for the further branch target instruction corresponds to the leading byte of the further branch target instruction, the subsequent instruction prefetch operation and the instruction decoding operation are suspended and disturbs the pipelined processing operation.